Lab: Design and Implementation of Magnitude Comparator

I. Objective:

· Build and observe functioning of a 2-bit magnitude comparator using basic logic gates.

· Build and observe functioning of a 8-bit magnitude comparator using IC 7485.

II. Parts List:

2-bit magnitude comparator:

· 5 – AND gates

· 2 – OR gates

· 2 – XOR gates

· 6 – NOT gates

· 1 – 1 KOhm resistor

· 4 – SPDT switches

· 3 – Digital probes

· 1 – VCC (5V)

· 1 – GND

8-bit magnitude comparator:

· 2 – 7485 ICs

· 1 – 1 KOhm resistor

· 16 – SPDT switches

· 3 – Digital probes

· 1 – VCC (5V)

· 1 – GND

III. Introduction:

The comparison of two numbers is an operator that determine one number is greater than, less than (or) equal to the other number. A magnitude comparator is a combinational circuit that compares two numbers A and B and determine their relative magnitude. The outcome of the comparator is specified by three binary variables that indicate whether A>B, A=B (or) A<B.

A = A3 A2 A1 A0

B = B3 B2 B1 B0

The equality of the two numbers and B is displayed in a combinational circuit designated by the symbol (A=B).

This indicates A greater than B, then inspect the relative magnitude of pairs of significant digits starting from most significant position. A is 0 and that of B is 0.

We have A<B, the sequential comparison can be expanded as

A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01

A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0

The same circuit can be used to compare the relative magnitude of two BCD digits.

Where, A = B is expanded as,

A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)

x3 x2 x1 x0

IV. Procedures:

1. Construct the circuit shown in Figure 1 using components listed in parts list for 2-bit magnitude comparator.

2. Change inputs A1, A0 and B1 B0 by changing SPDT switches and observe outputs (A=B, A > B, A < B) using digital probes.

3. Write down results using Table 1.

4. Construct the circuit shown in Figure 2 using components listed in parts list for 8-bit magnitude comparator.

5. Change inputs A3, A2, A1, A0 and B3. B2, B1, B0 by changing SPDT switches and observe outputs (A=B, A > B, A < B) using digital probes.

6. Write down results using Table 2.

Figure 1: 2-bit magnitude comparator

Table 1: 2-bit magnitude comparator results

Figure 2: 8-bit magnitude comparator

Table 2: 8-bit magnitude comparator results

V. Objective:

· Build and observe functioning of multiplexer and demultiplexer.

· Build and observe functioning of encoder and decoder.

VI. Parts List:

4:1 Multiplexer:

· 4 – AND gates

· 3 – OR gates

· 2 – NOT gates

· 1 – 1 KOhm resistor

· 6 – SPDT switches

· 1 – Digital probe

· 1 – VCC (5V)

· 1 – GND

1:4 Demultiplexer:

· 4 – AND gates

· 2 – NOT gates

· 1 – 1 KOhm resistor

· 3 – SPDT switches

· 4 – Digital probes

· 1 – VCC (5V)

· 1 – GND

Encoder:

· 9 – OR gates

· 1 – 1 KOhm resistor

· 7 – SPDT switches

· 3 – Digital probes

· 1 – VCC (5V)

· 1 – GND

Decoder:

· 4 – NAND gates

· 3 – NOT gates

· 1 – 1 KOhm resistor

· 3 – SPDT switches

· 4 – Digital probes

· 1 – VCC (5V)

· 1 – GND

VII. Introduction:

MULTIPLEXER:

Multiplexer means transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input line and n selection lines whose bit combination determine which input is selected.

DEMULTIPLEXER:

The function of Demultiplexer is in contrast to multiplexer function. It takes information from one line and distributes it to a given number of output lines. For this reason, the demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer.

In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select lines enable only one gate at a time and the data on the data input line will pass through the selected gate to the associated data output line.

ENCODER:

An encoder is a digital circuit that perform inverse operation of a decoder. An encoder has 2n input lines and n output lines. In encoder the output lines generates the binary code corresponding to the input value. In octal to binary encoder it has eight inputs, one for each octal digit and three output that generate the corresponding binary code. In encoder it is assumed that only one input has a value of one at any given time otherwise the circuit is meaningless. It has an ambiguila that when all inputs are zero the outputs are zero. The zero outputs can also be generated when D0 = 1.

DECODER:

A decoder is a multiple input multiple output logic circuit which converts coded input into coded output where input and output codes are different. The input code generally has fewer bits than the output code. Each input code word produces a different output code word i.e there is one to one mapping can be expressed in truth table. In the block diagram of decoder circuit, the encoded information is present as n input producing 2n possible outputs. 2n output values are from 0 through out 2n – 1.

VIII. Procedures:

7. Construct the circuit shown in Figure 1 using components listed in parts list for 4:1 multiplexer.

8. Set selection inputs (S1 and S0) and data inputs (D0, D1, D2 and D3) as shown in Table 1 by changing SPDT switches and observe output using a digital probe.

9. Write down “observed output” in Table 1. Validate if “observed output” is same as “predicted output”.

10. Construct the circuit shown in Figure 2 using components listed in parts list for 1:4 demultiplexer.

11. Set inputs S1, S0, and I/P as shown in Table 2 by changing SPDT switches and observe outputs using digital probes.

12. Write down “observed outputs” in Table 2. Validate if “observed outputs” are same as “predicted output”.

13. Construct the circuit shown in Figure 3 using components listed in parts list for the encoder.

14. Set inputs (Y1, Y2, Y3, Y4, Y5, Y6 and Y7) as shown in Table 3 by changing SPDT switches and observe output using digital probes.

15. Construct the circuit shown in Figure 4 using components listed in parts list for decoder.

16. Set inputs E, A, and B as shown in Table 4 by changing SPDT switches and observe outputs using digital probes.

17. Write down “observed outputs” in Table 4.

Figure 1: Circuit diagram for 4:1 multiplexer

Table 1: Results for 4:1 multiplexer

S1	S0	D0	D1	D2	D3	Predicted Output	Observed output
0	0	1	0	0	0	D0	D0
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